http://wiki.opalkelly.com/ 2012-05-17T23:58:54+00:00 http://wiki.opalkelly.com/ http://wiki.opalkelly.com/lib/images/favicon.ico text/html 2007-02-28T06:41:20+00:00 http://wiki.opalkelly.com/tutorial:part1?rev=1172644880&do=diff Approximate time to complete this part: 15 minutes This part of the tutorial will help you create a simple project to download to the XEM. This first project requires no communication between the PC and FPGA. Therefore, it can simply be downloaded to the XEM and run on its own. text/html 2007-02-28T18:58:15+00:00 http://wiki.opalkelly.com/tutorial:part2?rev=1172689095&do=diff Approximate time to complete this part: 30 minutes This part of the tutorial introduces the PC/FPGA connectivity provided by the FrontPanel HDL modules, the USB firmware loaded on the XEM3001, and the FrontPanel application. It is based on the First sample included with your XEM. The sample source files may be found in the Samples folder in your installation directory. text/html 2007-02-28T18:40:59+00:00 http://wiki.opalkelly.com/tutorial:part3?rev=1172688059&do=diff Approximate time to complete this part: 45 minutes This part of the tutorial introduces the PC/FPGA connectivity provided by the FrontPanel C++ API. The FrontPanel C++ API provides a powerful communication conduit between your C++ software application running on the PC and the HDL design on the FPGA. The same HDL components are used with the C++ API as were used with the FrontPanel application. text/html 2006-11-08T08:44:04+00:00 http://wiki.opalkelly.com/tutorial:part4?rev=1162975444&do=diff Approximate time to complete this part: 45 minutes In this part of the tutorial, the PC/FPGA connectivity shown in Part III will be performed in simulation by the free ModelSim XE III (available from Xilinx). We are also assuming that the user is working with the Verilog sample of the DES Tester for XEM3001v2. text/html 2006-11-19T02:20:36+00:00 http://wiki.opalkelly.com/tutorial:part4b?rev=1163902836&do=diff This is a brief overview of setting up a project in ActiveHDL 7.1 SP2 for Simulation of FrontPanel. For greater detail on the operation of FrontPanel Simulation, visit the full Part IV Tutorial. This tutorial will be describing how to setup a ActiveHDL Workspace/Design in a subdirectory of the Verilog DES tutorial presented in the preceding sections. Some notes on working with VHDL are at the bottom.